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git01.mediatek.com / filogic / atf / ee647e38368ca0410b82ce32d98fcb702e4878b4 / plat / xilinx / versal_net / plat_psci_pm.c
  1. b8eca3b fix(xilinx): check proc variable before use by Michal Simek · Fri Apr 19 12:16:46 2024 +0200
  2. 31488a3 feat(xilinx): add new state to identify cpu power down by Jay Buddhabhatti · Mon Sep 11 23:50:06 2023 -0700
  3. 10e71e4 feat(xilinx): request cpu power down from reset by Jay Buddhabhatti · Mon Jun 19 05:08:54 2023 -0700
  4. b7bb1ed fix(versal-net): use arm common GIC handlers by Jay Buddhabhatti · Thu Oct 05 21:55:28 2023 -0700
  5. 7d0623a chore(xilinx): follow kernel doc format for functional documentation by Prasad Kummari · Fri Jun 09 14:32:00 2023 +0530
  6. 0129707 feat(xilinx): sync copyright format by Michal Simek · Tue Apr 25 14:14:06 2023 +0200
  7. 6cd94be fix(versal-net): correct aff level for cpu off by Jay Buddhabhatti · Wed Mar 22 22:44:16 2023 -0700
  8. 7c5adef fix(versal-net): fix setting power down state by Jay Buddhabhatti · Thu Dec 29 21:58:35 2022 -0800
  9. c6daff0 feat(versal-net): add support for platform management by Jay Buddhabhatti · Mon Sep 05 02:56:32 2022 -0700