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git01.mediatek.com / filogic / atf / eaed76b03c6efea4a460512ba88f3eef0d58c706 / plat / intel / soc / common / socfpga_delay_timer.c
  1. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · 12 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years ago
  3. 2f2b61c fix(intel): remove unused printout by Sieu Mun Tang · 2 years, 2 months ago
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
  5. 64d2b2f plat: intel: Additional instruction required to enable global timer by Tien Hock Loh · 4 years, 2 months ago
  6. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago[Renamed (87%) from plat/intel/soc/agilex/socfpga_delay_timer.c]
  7. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago