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git01.mediatek.com / filogic / atf / ea1faa2b4b2e9ec88cadd868d6f1e0d51419691b / plat / nvidia / tegra / soc / t210 / platform_t210.mk
  1. 29b4665 Tegra: compile PMC driver for Tegra132/Tegra210 platforms by Varun Wadekar · 6 years ago
  2. be57abb spd: trusty: memmap trusty's code memory before peeking by Varun Wadekar · 6 years ago
  3. a1ad9b7 Tegra210: SiP handlers to allow PMC access by kalyani chidambaram · 6 years ago
  4. ba31328 Tegra210: support for cluster idle from the CPU by Varun Wadekar · 6 years ago
  5. c6041c9 Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs by Varun Wadekar · 6 years ago
  6. 50a3303 Tegra: console driver compilation from platform makefiles by Varun Wadekar · 7 years ago
  7. 24ea656 Tegra210: increase number of dynamic memory mappings by Varun Wadekar · 7 years ago
  8. 7baa94a Tegra210: increase MAX_XLAT_TABLES and MAX_MMAP_REGIONS by Varun Wadekar · 7 years ago
  9. a6a357f Tegra210: bpmp: power management interface by Varun Wadekar · 7 years ago
  10. 21eea97 Tegra210B01: SE1 and SE2/PKA1 context save (atomic) by Marvin Hsu · 7 years ago
  11. 9f4a7d3 Tegra: support for native GICv2 drivers by Varun Wadekar · 6 years ago
  12. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  13. 4d160ac Tegra: memmap Tegra micro-seconds timer controller by Steven Kao · 8 years ago
  14. 1108fc6 plat/tegra: Enable Cortex-A53 erratum 855873 workaround by Andre Przywara · 8 years ago
  15. ed3c62b Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs by Varun Wadekar · 7 years ago
  16. 1edb882 Tegra210: new TZDRAM base address by Varun Wadekar · 8 years ago
  17. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · 9 years ago
  18. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · 9 years ago
  19. 7a9a285 Tegra: Memory Controller Driver (v1) by Varun Wadekar · 9 years ago
  20. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  21. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · 9 years ago
  22. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · 9 years ago
  23. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · 9 years ago
  24. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  25. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  26. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  27. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago