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git01.mediatek.com / filogic / atf / e96e95361f1ff77dd7d048cf6cac923ca55dea1d / plat / arm / board / arm_fpga
  1. e1cc130 GICv3: GIC-600: Detect GIC-600 at runtime by Andre Przywara · Wed Mar 25 15:50:38 2020 +0000
  2. 7ec175e Rename Cortex Hercules Files to Cortex A78 by Jimmy Brisson · Mon Jun 01 16:49:34 2020 -0500
  3. db96806 arm_fpga: Read UART address from DT by Andre Przywara · Thu Apr 09 10:25:43 2020 +0100
  4. b351481 arm_fpga: Read GICD and GICR base addresses from DT by Andre Przywara · Fri Jan 24 15:46:05 2020 +0000
  5. eec45eb arm_fpga: Read generic timer counter frequency from DT by Andre Przywara · Fri Jan 24 15:02:27 2020 +0000
  6. 8b50525 arm_fpga: Use Generic UART by Andre Przywara · Thu Apr 09 10:10:09 2020 +0100
  7. 2f18ea2 arm_fpga: Remove bogus timer initialisation by Andre Przywara · Thu Apr 09 11:27:21 2020 +0100
  8. b21cad7 arm_fpga: adapt to new way of including gicv3 files by Manish Pandey · Fri Apr 03 18:59:20 2020 +0100
  9. 25786a3 Fix coverity defects found on the FPGA port. by Javier Almansa Sobrino · Thu Apr 02 12:36:16 2020 +0100
  10. 7fbb9b5 plat/arm/board/arm_fpga: Compile with additional CPU libraries by Oliver Swede · Wed Jan 15 10:20:09 2020 +0000
  11. 735fcf3 plat/arm/board/arm_fpga: Enable position-independent execution by Oliver Swede · Tue Jan 07 14:43:01 2020 +0000
  12. 3769b3f plat/arm/board/arm_fpga: Enable port for alternative cluster configurations by Oliver Swede · Mon Dec 16 14:08:27 2019 +0000
  13. b51da81 plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller by Oliver Swede · Tue Dec 03 14:08:21 2019 +0000
  14. 20e0137 plat/arm/board/arm_fpga: Initialize the System Counter by Oliver Swede · Mon Dec 02 13:33:40 2019 +0000
  15. 6e86c5a plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images by Oliver Swede · Mon Dec 02 13:21:52 2019 +0000
  16. f94e2ee plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow by Oliver Swede · Mon Nov 11 11:32:32 2019 +0000
  17. 8fed2fe plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image by Oliver Swede · Mon Nov 11 11:11:06 2019 +0000