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git01.mediatek.com / filogic / atf / e8b6b800ddcb805d8289f9e2577625553364f973 / plat / nvidia / tegra / soc / t194 / plat_trampoline.S
  1. 75c9443 Tegra: smmu: remove context save sequence by Pritesh Raithatha · Fri Aug 03 15:48:15 2018 +0530
  2. 66f9ff6 Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list by Pritesh Raithatha · Thu Apr 19 13:11:43 2018 +0530
  3. fc8f2c5 Tegra194: smmu: add support for backup multiple smmu regs by Pritesh Raithatha · Thu Oct 26 17:06:02 2017 +0530
  4. da865de Tegra194: save system suspend entry marker to TZDRAM by Varun Wadekar · Fri Nov 10 13:27:29 2017 -0800
  5. e0c222f Tegra194: helper functions for CPU rst handler and SMMU ctx offset by Varun Wadekar · Fri Nov 10 13:23:34 2017 -0800
  6. 362a6b2 Tegra194: cleanup references to Tegra186 by Varun Wadekar · Fri Nov 10 11:04:42 2017 -0800
  7. fa871a6 Tegra194: Fix TEGRA186_SMMU_CTX_SIZE by Stefan Kristiansson · Mon Mar 20 14:19:46 2017 +0200
  8. ecd6a5a Tegra194: base commit for the platform by Varun Wadekar · Mon Apr 09 17:48:58 2018 -0700