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git01.mediatek.com / filogic / atf / e768ba203770dec6a5191ad90326f869ca345c9d / drivers / marvell / ap807_clocks_init.c
  1. c035d9d ble: ap807: improve PLL configuration sequence by Alex Leibovich · Mon Feb 25 13:13:48 2019 +0200
  2. 605162e ble: ap807: clean-up PLL configuration sequence by Alex Leibovich · Sun Feb 10 15:08:25 2019 +0200
  3. a5d0627 plat: marvell: add support for PLL 2.2GHz mode by Grzegorz Jaszczyk · Thu Dec 20 17:13:19 2018 +0100
  4. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  5. 9a772df ble: ap807: Switch to PLL mode and update CPU frequency by Christine Gharzuzi · Mon Jun 25 13:39:37 2018 +0300