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git01.mediatek.com / filogic / atf / e43ba98fe98ac78454c2057e57ddbbc6baf093d5 / plat / intel / soc / stratix10 / include / s10_clock_manager.h
  1. 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · 2 years, 2 months ago
  2. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
  3. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · 2 years, 2 months ago
  4. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 4 years, 8 months ago
  5. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  6. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · 5 years ago
  7. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · 5 years ago