Log - e294ec6a2074ecb9b909b41d1709cfb2fd779729 - filogic/atf

4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · Fri Aug 21 15:56:02 2015 +0530
bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · Mon Jul 27 13:00:50 2015 +0530
254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · Thu Jul 23 10:07:54 2015 +0530
5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · Tue Jul 21 11:53:35 2015 +0530
d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · Thu Jul 16 09:46:28 2015 +0530
6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · Thu Jul 16 11:58:19 2015 +0530
071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · Wed Jul 08 17:42:02 2015 +0530
81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · Fri Jul 03 16:31:28 2015 +0530
b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530