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git01.mediatek.com / filogic / atf / e18cf33418501c62a5d0dba0ff5dba69affb598d / include / drivers / clk.h
  1. a55326b feat(clk): add set_rate callback by Ghennadi Procopciuc · Sat Jun 01 00:04:31 2024 +0300
  2. 52f8b01 feat(clk): add set_parent callback by Ghennadi Procopciuc · Mon Jun 03 09:16:41 2024 +0300
  3. 8aac307 feat(clk): add a minimal clock framework by Gabriel Fernandez · Tue Oct 13 09:36:25 2020 +0200