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git01.mediatek.com / filogic / atf / e164e26a5838ea7cec57a02a8bcf5bad1ad5874a / plat / xilinx / versal / include / versal_def.h
  1. 5586151 Create separate header for ARM specific SMCCC defines by Manish V Badarkhe · Fri Mar 27 13:25:51 2020 +0000
  2. 9156ffd xilinx: versal: PLM to ATF handover by Venkatesh Yadav Abbarapu · Wed Jan 22 21:23:20 2020 -0700
  3. 2f4cc71 xilinx: versal: Wire silicon default setup by Siva Durga Prasad Paladugu · Fri May 03 16:35:25 2019 +0530
  4. 41dd096 plat: xilinx: versal: Dont set IOU switch clock by Siva Durga Prasad Paladugu · Tue Jun 25 17:48:27 2019 +0530
  5. 10161e5 arm64: versal: Adjust cpu clock for versal virtual by Siva Durga Prasad Paladugu · Sat Apr 27 11:23:20 2019 +0530
  6. 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · Wed Feb 27 18:44:55 2019 +0530
  7. fe0e10a xilinx: versal: Add support for suspend related APIs by Tejas Patel · Sun Dec 08 23:29:44 2019 -0800
  8. 354fe57 xilinx: Add support to send PM API to PMC using IPI for versal by Tejas Patel · Fri Dec 14 00:55:37 2018 -0800
  9. 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · Fri Dec 14 00:55:30 2018 -0800[Renamed (97%) from plat/xilinx/versal/versal_def.h]
  10. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  11. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · Tue Sep 25 18:44:58 2018 +0530