Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / e026eea4c6c15d9bef456746b61eb2b40fb59a2b / plat / intel / soc / stratix10 / include / s10_clock_manager.h
  1. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · 2 years, 4 months ago
  2. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 5 years ago
  3. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  4. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · 6 years ago
  5. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · 6 years ago