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git01.mediatek.com / filogic / atf / dfcf0944f487ae5c4f9a9840a53176374ecc659c / plat / nvidia / tegra / soc / t194 / plat_secondary.c
  1. 9de77f6 Tegra194: add redundancy checks for MMIO writes by Anthony Zhou · Wed Nov 13 18:36:07 2019 +0800
  2. 254b57d Tegra194: store TZDRAM base/size to scratch registers by Jeetesh Burman · Fri Jul 06 19:58:30 2018 +0530
  3. e0c222f Tegra194: helper functions for CPU rst handler and SMMU ctx offset by Varun Wadekar · Fri Nov 10 13:23:34 2017 -0800
  4. 362a6b2 Tegra194: cleanup references to Tegra186 by Varun Wadekar · Fri Nov 10 11:04:42 2017 -0800
  5. 4607f17 Tegra194: rename secure scratch register macros by Steven Kao · Mon Oct 23 18:35:14 2017 +0800
  6. 8bf6d4e Tegra194: fix defects flagged by MISRA scan by Anthony Zhou · Wed Sep 20 17:44:43 2017 +0800
  7. 2cdb678 Tegra194: Enable MCE driver by Steven Kao · Thu Jan 05 17:04:40 2017 +0800
  8. ecd6a5a Tegra194: base commit for the platform by Varun Wadekar · Mon Apr 09 17:48:58 2018 -0700