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git01.mediatek.com / filogic / atf / dfcf0944f487ae5c4f9a9840a53176374ecc659c / plat / nvidia / tegra / include / plat_macros.S
  1. 4151af9 Tegra: print GICC registers conditionally by Varun Wadekar · Fri Oct 04 11:40:56 2019 -0700
  2. ffbf32a Makefile: remove extra include paths in INCLUDES by Ambroise Vincent · Thu Mar 28 09:01:18 2019 +0000
  3. 4fe43a3 Tegra: fix offset used to dump GICD registers from crash handler by Varun Wadekar · Tue Jan 02 14:10:18 2018 -0800
  4. 9f4a7d3 Tegra: support for native GICv2 drivers by Varun Wadekar · Fri Oct 19 11:42:28 2018 -0700
  5. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  6. 6bf7c6b tegra: Migrate to new interfaces by Antonio Nino Diaz · Mon Sep 24 17:16:05 2018 +0100
  7. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  8. bfc6605 Tegra: fix logic to calculate GICD_ISPENDR register address by Varun Wadekar · Tue Aug 23 14:01:19 2016 -0700
  9. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · Thu Nov 26 15:47:53 2015 +0100
  10. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530