Log - ddf3abbae949baeca7e7a66c00b790554de9359e - filogic/atf

bd17eae refactor(context mgmt): remove registers accessible only from secure state from EL2 context by Zelalem Aweke · Wed Nov 03 13:31:53 2021 -0500
72b69b8 refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags by Jayanth Dodderi Chidanand · Wed Jan 26 17:14:43 2022 +0000
13ae0f4 fix(amu): fault handling on EL2 context switch by Jayanth Dodderi Chidanand · Thu Nov 25 14:59:30 2021 +0000
b6301e6 feat(rme): add context management changes for FEAT_RME by Zelalem Aweke · Fri Jul 09 17:54:30 2021 -0500
f91e59f feat(hcx): add build option to enable FEAT_HCX by johpow01 · Wed Aug 04 19:38:18 2021 -0500
c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
cf784f7 Fix: Remove save/restore of EL2 timer registers by Max Shvetsov · Wed Mar 31 19:00:38 2021 +0100
fba2572 Fix exception handlers in BL31: Use DSB to synchronize pending EA by Madhukar Pappireddy · Fri Jul 24 03:27:12 2020 -0500
2b0ee97 el3_runtime: Rearrange context offset of EL1 sys registers by Manish V Badarkhe · Tue Jul 28 07:22:30 2020 +0100
0c16abd Fix exception in save/restore of EL2 registers. by Max Shvetsov · Wed May 13 18:15:39 2020 +0100
1962891 context: TPIDR_EL2 register not saved/restored by Olivier Deprez · Fri Mar 20 14:22:05 2020 +0100
c9e2c92 SPMD: Adds partially supported EL2 registers. by Max Shvetsov · Mon Feb 17 16:15:47 2020 +0000
bdf502d SPMD: save/restore EL2 system registers. by Max Shvetsov · Tue Feb 25 13:56:19 2020 +0000
91d8061 coverity: fix MISRA violations by Zelalem · Wed Feb 12 10:37:03 2020 -0600
f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
1c7c13a Enable MTE support in both secure and non-secure worlds by Justin Chadwell · Thu Jul 18 14:25:33 2019 +0100
503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
13adfb1 Cleanup context handling library by Antonio Nino Diaz · Wed Jan 30 20:41:31 2019 +0000
e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
32ceef5 SDEI: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
bb1fd5b SDEI: Ensure SDEI handler executes with CVE-2018-3639 mitigation enabled by Dimitris Papastamos · Thu Jun 07 11:29:15 2018 +0100
ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
96c7df0 AArch64: Introduce External Abort handling by Jeenu Viswambharan · Thu Nov 30 12:54:15 2017 +0000
b63c6f1 Optimize/cleanup BPIALL workaround by Dimitris Papastamos · Thu Jan 11 15:29:36 2018 +0000
c52ebdc Workaround for CVE-2017-5715 on Cortex A73 and A75 by Dimitris Papastamos · Mon Dec 18 13:46:21 2017 +0000
5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · Fri Oct 20 11:30:57 2017 +0100
4168f2f Init and save / restore of PMCR_EL0 / PMCR by David Cunado · Mon Oct 02 17:41:39 2017 +0100
ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000