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git01.mediatek.com / filogic / atf / dd9af9b451fec08a330f5bc9a90049fa81edd001 / plat / nxp / common / include / default
  1. 7e20b7a feat(layerscape): add soc helper macro definition for chassis 3 by Jiafei Pan · Fri Feb 18 15:29:47 2022 +0800
  2. 21a3284 feat(layerscape): define more chassis 3 hardware address by Jiafei Pan · Fri Feb 18 15:24:27 2022 +0800
  3. d81dc46 feat(nxp/common/io): add ifc nor and nand as io devices by Jiafei Pan · Thu Oct 21 16:30:12 2021 +0800
  4. be9efe5 feat(nxp/common/rcpm): add RCPM2 registers definition by Jiafei Pan · Thu Oct 21 15:28:37 2021 +0800
  5. 64e2ba7 feat(plat/nxp/common): add EESR register definition by Jiafei Pan · Mon Sep 27 12:18:41 2021 +0800
  6. 0a7cf57 feat(plat/nxp/common): define default SD buffer by Jiafei Pan · Fri Sep 10 19:19:32 2021 +0800
  7. 40b6d86 feat(plat/nxp/common): add SecMon register definition for ch_3_2 by Jiafei Pan · Fri Sep 10 19:13:27 2021 +0800
  8. f4a5605 feat(plat/nxp/common): add CCI and EPU address definition by Jiafei Pan · Fri Sep 10 15:36:37 2021 +0800
  9. 82bd843 nxp: deflt hdr files for soc & their platforms by Pankaj Gupta · Wed Dec 09 14:02:41 2020 +0530