Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / dd19b2e6f0c41d606c0814fed0475bf919ab8196 / plat / intel / soc / stratix10 / include / s10_clock_manager.h
  1. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · 1 year, 2 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years ago
  3. 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · 2 years, 2 months ago
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
  5. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · 2 years, 2 months ago
  6. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 4 years, 8 months ago
  7. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  8. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · 5 years ago
  9. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · 5 years ago