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git01.mediatek.com / filogic / atf / dd19b2e6f0c41d606c0814fed0475bf919ab8196 / plat / intel / soc / n5x / include / socfpga_plat_def.h
  1. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · 1 year, 2 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years ago
  3. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years, 2 months ago
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
  5. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years, 2 months ago
  6. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 4 months ago
  7. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 4 months ago