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git01.mediatek.com / filogic / atf / d9489b10bd6e3872c247cdd8bc581816c5e27b5d / plat / intel / soc / common / socfpga_delay_timer.c
  1. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · Fri Jul 07 17:15:26 2023 +0800
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · Thu Jun 23 18:05:02 2022 +0800
  3. 2f2b61c fix(intel): remove unused printout by Sieu Mun Tang · Fri May 13 16:42:42 2022 +0800
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  5. 64d2b2f plat: intel: Additional instruction required to enable global timer by Tien Hock Loh · Mon May 11 01:12:03 2020 -0700
  6. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 15:21:20 2019 +0800[Renamed (87%) from plat/intel/soc/agilex/socfpga_delay_timer.c]
  7. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · Thu Jun 27 11:34:03 2019 +0800