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git01.mediatek.com / filogic / atf / cf7a14028f4798c4c08a81bc97a11a8c80a19ba4 / plat / arm / board / rde1edge / include
  1. 0964159 plat/sgi: refactor SDEI specific macros by Thomas Abraham · Tue Feb 16 12:23:56 2021 +0530
  2. ce79bca plat/arm/sgi: refactor header file inclusions by Aditya Angadi · Wed Nov 18 08:32:30 2020 +0530
  3. 64c9645 plat/arm/sgi: move GIC related constants to board files by Vijayenthiran Subramaniam · Mon Feb 03 12:14:01 2020 +0530
  4. 7b424ba drivers/mhu: derive doorbell base address by Aditya Angadi · Tue Dec 31 10:14:32 2019 +0530
  5. 4287c0c Unify type of "cpu_idx" across PSCI module. by Deepika Bhavnani · Fri Dec 13 10:23:18 2019 -0600
  6. 8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
  7. 69bebd8 n1sdp: add code for DDR ECC enablement and BL33 copy to DDR by Manoj Kumar · Fri Jun 21 17:07:13 2019 +0100
  8. 0d31688 plat/arm: mhu: make mhu driver generic by Masahisa Kojima · Thu Mar 07 11:23:42 2019 +0900
  9. 533b554 board/rde1edge: rename sgiclarkh to rde1edge by Chandni Cherukuri · Fri Feb 22 16:44:49 2019 +0530