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git01.mediatek.com / filogic / atf / cea0c26d4cfa05b28317dbc6a1bbf9ad804f8387 / plat / xilinx / versal_net / versal_net_gicv3.c
  1. 0129707 feat(xilinx): sync copyright format by Michal Simek · Tue Apr 25 14:14:06 2023 +0200
  2. 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · Fri Apr 14 08:43:51 2023 +0200
  3. 6a44ad0 refactor(xilinx): rename gic macros to make common by Jay Buddhabhatti · Tue Feb 28 01:23:04 2023 -0800
  4. 33bfc5e build: always prefix section names with `.` by Chris Kay · Tue Feb 14 11:30:04 2023 +0000
  5. d517f7b fix(versal-net): populate gic v3 rdist data statically by Jay Buddhabhatti · Mon Jan 23 23:32:35 2023 -0800
  6. c6daff0 feat(versal-net): add support for platform management by Jay Buddhabhatti · Mon Sep 05 02:56:32 2022 -0700
  7. 9179436 feat(versal-net): add support for Xilinx Versal NET platform by Michal Simek · Wed Aug 31 16:45:14 2022 +0200