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git01.mediatek.com / filogic / atf / cdd3e72eb0ff9f437408708de9ee85b336cf4e73 / plat / intel / soc / n5x / platform.mk
  1. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago
  2. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  3. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 2 years, 5 months ago
  4. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years, 6 months ago
  5. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 3 years, 6 months ago
  6. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 9 months ago
  7. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 5 months ago
  8. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 9 months ago