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git01.mediatek.com / filogic / atf / cb2dd3a587b09418ed3a3dc3d46d8744a511d8e6 / plat / intel / soc / common / socfpga_delay_timer.c
  1. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 4 months ago
  2. 2f2b61c fix(intel): remove unused printout by Sieu Mun Tang · 2 years, 6 months ago
  3. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 7 months ago
  4. 64d2b2f plat: intel: Additional instruction required to enable global timer by Tien Hock Loh · 4 years, 6 months ago
  5. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago[Renamed (87%) from plat/intel/soc/agilex/socfpga_delay_timer.c]
  6. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago