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git01.mediatek.com / filogic / atf / c883ce045b3529d7c5ff7de8f7dc376ddee4bd58 / drivers / marvell / ap807_clocks_init.c
  1. c035d9d ble: ap807: improve PLL configuration sequence by Alex Leibovich · 5 years ago
  2. 605162e ble: ap807: clean-up PLL configuration sequence by Alex Leibovich · 5 years ago
  3. a5d0627 plat: marvell: add support for PLL 2.2GHz mode by Grzegorz Jaszczyk · 6 years ago
  4. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  5. 9a772df ble: ap807: Switch to PLL mode and update CPU frequency by Christine Gharzuzi · 6 years ago