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git01.mediatek.com / filogic / atf / c7a7cc34bc39abff227ebeed012a83f118d2fe1f / plat / rockchip / rk3399 / drivers / pmu / m0_ctl.c
  1. 2b558a6 Update rockchip platform to not rely on undefined overflow behaviour by Justin Chadwell · 5 years ago
  2. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  3. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · 6 years ago
  4. e363146 Fix order of remaining platform #includes by Isla Mitchell · 7 years ago
  5. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  6. 22a9871 rockchip: rk3399: Clean up and seprate secure parts from SoC codes by Xing Zheng · 7 years ago
  7. 8140b7d rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error by Lin Huang · 8 years ago
  8. 61230b0 FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init by Xing Zheng · 8 years ago
  9. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · 8 years ago
  10. c8e5c78 rockchip: rk3399: fix hang in ddr set rate by Derek Basehore · 7 years ago
  11. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · 8 years ago