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git01.mediatek.com / filogic / atf / c5586d16a019c1feb8f7315818156aef1025cdf3 / plat / nxp / common / setup
  1. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  2. 08b1265 fix(layerscape): fix coverity issue by Jiafei Pan · Tue Mar 29 15:01:09 2022 +0800
  3. b9d543c feat(ls1088a): add new SoC platform ls1088a by Jiafei Pan · Fri Feb 18 15:26:08 2022 +0800
  4. 025660f fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically by Biwen Li · Mon Jan 11 11:11:44 2021 +0800
  5. f0fe683 fix(nxp/common/setup): increase soc name maximum length by Jiafei Pan · Thu Oct 21 17:03:04 2021 +0800
  6. d81dc46 feat(nxp/common/io): add ifc nor and nand as io devices by Jiafei Pan · Thu Oct 21 16:30:12 2021 +0800
  7. 6266180 fix(nxp/common/setup): fix total dram size checking by Jiafei Pan · Thu Oct 21 15:17:51 2021 +0800
  8. e5dcf98 fix: libc: use long for 64-bit types on aarch64 by Scott Branden · Tue Aug 25 13:49:32 2020 -0700
  9. def7edc feat(plat/nxp/common): define common macro for ARM registers by Jiafei Pan · Fri Sep 10 18:54:56 2021 +0800
  10. b27ac80 refactor(plat/nxp): refine api to read SVR register by Jiafei Pan · Tue Jul 20 17:14:32 2021 +0800
  11. 988bbb2 nxp: platform files for bl2 and bl31 setup by Pankaj Gupta · Wed Dec 09 14:02:40 2020 +0530