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git01.mediatek.com / filogic / atf / c4a1a07e2878baba15c47bb3ab398a317ace86fa / plat / nvidia / tegra / common / tegra_sip_calls.c
  1. e363146 Fix order of remaining platform #includes by Isla Mitchell · Fri Jul 14 10:46:32 2017 +0100
  2. a59a7c5 Tegra: memctrl: check GPU reset state from common place by Varun Wadekar · Wed Apr 26 08:31:50 2017 -0700
  3. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  4. 14f3957 Tegra186: Support AARCH32/64 encoding for MCE calls by Varun Wadekar · Mon Apr 17 11:54:33 2017 -0700
  5. b4a7294 Tegra: Add support for fake system suspend by Vignesh Radhakrishnan · Fri Mar 03 10:58:05 2017 -0800
  6. e0f3dfd Tegra: SiP: 64-bit address for Video Memory base by Harvey Hsieh · Tue Oct 11 18:59:52 2016 +0800
  7. dc79930 Tegra: implement FIQ interrupt handler by Varun Wadekar · Mon Dec 28 16:36:42 2015 -0800
  8. 2330edd Tegra: allow SiP smc calls from Secure World by Wayne Lin · Thu Mar 31 13:49:09 2016 -0700
  9. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · Wed Dec 09 18:18:53 2015 -0800[Renamed (82%) from plat/nvidia/tegra/soc/t210/plat_sip_calls.c]
  10. 3acb2b0 Merge pull request #845 from vwadekar/tegra-changes-from-downstream-v1 by davidcunado-arm · Thu Feb 23 17:30:54 2017 +0000