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git01.mediatek.com / filogic / atf / c09e7bd781765fb466479f2fe92a06e6423d13d2 / plat / xilinx / versal / aarch64
  1. e7604f3 feat(versal): remove the time stamp configuration by Venkatesh Yadav Abbarapu · Sat Jan 29 23:17:25 2022 -0700
  2. 9156ffd xilinx: versal: PLM to ATF handover by Venkatesh Yadav Abbarapu · Wed Jan 22 21:23:20 2020 -0700
  3. 41dd096 plat: xilinx: versal: Dont set IOU switch clock by Siva Durga Prasad Paladugu · Tue Jun 25 17:48:27 2019 +0530
  4. 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · Wed Feb 27 18:44:55 2019 +0530
  5. 354fe57 xilinx: Add support to send PM API to PMC using IPI for versal by Tejas Patel · Fri Dec 14 00:55:37 2018 -0800
  6. 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · Fri Dec 14 00:55:30 2018 -0800
  7. 6940996 plat: xilinx: versal: Move versal_private.h to include directory by Tejas Patel · Fri Dec 14 00:55:29 2018 -0800
  8. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  9. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · Tue Sep 25 18:44:58 2018 +0530