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git01.mediatek.com / filogic / atf / b619f491a975be063ab2d3cefa4dd004a1d39291 / lib / cpus / aarch64 / cpu_helpers.S
  1. 3868b23 fix(cpus): assert invalid cpu_ops obtained by Thaddeus Serna · Wed Jul 19 13:59:24 2023 -0500
  2. 06236c9 refactor(cpus): convert print_errata_status to C by Boyan Karatotev · Wed Jan 25 18:50:10 2023 +0000
  3. 5d38cb3 refactor(cpus): rename errata_report.h to errata.h by Boyan Karatotev · Fri Jan 27 09:37:07 2023 +0000
  4. e7d7c27 refactor(cpus): move cpu_ops field defines to a header by Boyan Karatotev · Wed Jan 25 16:55:18 2023 +0000
  5. 667db2c Merge changes from topic "bk/errata_refactor" into integration by Manish Pandey · Mon Mar 20 16:45:08 2023 +0100
  6. cc30ccf chore(cpus): remove redundant asserts by Boyan Karatotev · Fri Jan 27 10:51:27 2023 +0000
  7. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  8. caa2e05 fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 by Bipin Ravi · Wed Feb 23 23:45:50 2022 -0600
  9. 7d0299f fix: random typos in tf-a code base by Olivier Deprez · Tue May 25 12:06:03 2021 +0200
  10. e1ecd23 arm_fpga: Add support for unknown MPIDs by Javier Almansa Sobrino · Thu Aug 20 18:48:09 2020 +0100
  11. 718c876 lib: cpus: sanity check pointers before use by Varun Wadekar · Tue Oct 01 09:34:10 2019 -0700
  12. 94accd3 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · Tue Aug 20 15:51:24 2019 -0500
  13. 4d034c5 Tegra: Support for scatterfile for the BL31 image by Varun Wadekar · Fri Jan 11 14:47:48 2019 -0800
  14. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  15. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  16. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · Fri Apr 06 15:29:34 2018 +0100
  17. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  18. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  19. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  20. 815faa8 Use a callee-saved register to be AAPCS-compliant by dp-arm · Fri May 05 12:21:03 2017 +0100
  21. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  22. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · Thu Apr 20 09:58:28 2017 +0100
  23. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · Thu Oct 06 16:54:53 2016 +0100
  24. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  25. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  26. 1f5f812 Correct system include order by David Cunado · Tue Jan 17 14:40:15 2017 +0000
  27. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  28. 6b28c57 Make cpu operations warning a VERBOSE print by Soby Mathew · Mon Mar 21 10:36:47 2016 +0000
  29. d481759 Disable non-temporal hint on Cortex-A53/57 by Sandrine Bailleux · Wed Jan 13 14:57:38 2016 +0000
  30. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · Tue Mar 24 14:03:57 2015 +0000
  31. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  32. b5a6304 Fix the Cortex-A57 reset handler register usage by Soby Mathew · Thu Jan 29 12:00:58 2015 +0000
  33. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  34. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · Tue Nov 18 10:14:14 2014 +0000
  35. c088433 Apply errata workarounds only when major/minor revisions match. by Soby Mathew · Mon Sep 22 12:11:36 2014 +0100
  36. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  37. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  38. f1785fd Add platform API for reset handling by Soby Mathew · Thu Aug 14 12:22:32 2014 +0100
  39. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100