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git01.mediatek.com / filogic / atf / b44eda5a20d1c84f73f1a493189a5256686a70cd / plat / nvidia / tegra / common / aarch64
  1. 91b11c3 Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR* by Eleanor Bonnici · 7 years ago
  2. b4c75e9 Add new alignment parameter to func assembler macro by Julius Werner · 7 years ago
  3. e363146 Fix order of remaining platform #includes by Isla Mitchell · 7 years ago
  4. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · 7 years ago
  5. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  6. 4e6ae18 Tegra: no need to re-init the same console by Varun Wadekar · 8 years ago
  7. 2bb9f47 Tegra: replace ASM signed tests with unsigned by Douglas Raillard · 8 years ago
  8. 69ce101 Tegra: enable ECC/Parity protection for Cortex-A57 CPUs by Varun Wadekar · 9 years ago
  9. 25e658e Tegra: include platform_def.h to access UART macros by Varun Wadekar · 9 years ago
  10. 1ec441e Tegra: relocate code to BL31_BASE during cold boot by Varun Wadekar · 9 years ago
  11. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · 9 years ago
  12. 39f87d1 Tegra: use ClusterId for calculating core position by Varun Wadekar · 9 years ago
  13. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  14. e7ae6db Disable PL011 UART before configuring it by Juan Castillo · 9 years ago
  15. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · 9 years ago
  16. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  17. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  18. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 10 years ago