- a40141d refactor(amu): detect architected counters at runtime by Chris Kay · 3 years, 6 months ago
- a5fde28 refactor(amu): factor out register accesses by Chris Kay · 3 years, 6 months ago
- b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 3 years, 1 month ago
- 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · 3 years, 4 months ago
- 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 3 years, 4 months ago
- f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · 3 years, 5 months ago
- f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 3 years, 4 months ago
- 514e59c Add PIE support for AARCH32 by Yann Gautier · 4 years, 1 month ago
- e57bce8 Avoid the use of linker *_SIZE__ macros by Yann Gautier · 4 years, 3 months ago
- 08fec33 arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms by Chris Kay · 3 years, 8 months ago
- fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · 4 years, 2 months ago
- f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years ago
- 5c29cba aarch64/arm: Add compiler barrier to barrier instructions by Andre Przywara · 4 years, 1 month ago
- ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · 4 years, 4 months ago
- 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · 4 years, 4 months ago
- 90d6532 Provide a hint to power controller for DSU cluster power down by Madhukar Pappireddy · 5 years ago
- 019b4f8 locks: bakery: use is_dcache_enabled() helper by Masahiro Yamada · 4 years, 8 months ago
- a5c6636 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · 4 years, 8 months ago
- 84d681f Merge "el3_entrypoint_common: avoid overwriting arg3" into integration by Manish Pandey · 4 years, 8 months ago
- bfe7bb6 Use Speculation Barrier instruction for v8.5 cores by Madhukar Pappireddy · 4 years, 8 months ago
- fcbcd6f aarch32: stop speculative execution past exception returns by Madhukar Pappireddy · 4 years, 9 months ago
- c241b57 el3_entrypoint_common: avoid overwriting arg3 by Yann Gautier · 4 years, 10 months ago
- 20be077 Changes to support updated register usage in SMCCC v1.2 by Madhukar Pappireddy · 5 years ago
- d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 5 years ago
- 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 5 years ago
- 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · 5 years ago
- 5553417 SSBS: init SPSR register with default SSBS value by John Tsichritzis · 5 years ago
- 35e08da console: update skeleton by Ambroise Vincent · 5 years ago
- 007d745 arch: add some defines for generic timer registers by Yann Gautier · 6 years ago
- 457c64e aarch32: Allow compiling with soft-float toolchain by Manish Pandey · 6 years ago
- 0a0ca8b Console: remove deprecated finish_console_register by Ambroise Vincent · 6 years ago
- f5fdfbc Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · 6 years ago
- 404184d Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd by Antonio Niño Díaz · 6 years ago
- 078e66f plat/arm: Support for Cortex A5 in FVP Versatile Express platform by Usama Arif · 6 years ago
- b69ac08 Division functionality for cores that dont have divide hardware. by Usama Arif · 6 years ago
- 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
- d29d21e drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · 6 years ago
- c326c34 xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · 6 years ago
- e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
- 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 6 years ago