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git01.mediatek.com / filogic / atf / b37f4ea31fea86079960af1a52d6bcde66da4ee3 / include / lib / cpus
  1. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  2. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  3. 9fe40fd Fix MISRA defects in workaround and errata framework by Antonio Nino Diaz · Thu Oct 25 17:11:02 2018 +0100
  4. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  5. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  6. b561536 plat/arm: relocate the jump_if_cpu_midr macro. by Deepak Pandey · Thu Oct 11 13:44:43 2018 +0530
  7. dc9fab1 Remove all other deprecated interfaces and files by Antonio Nino Diaz · Tue Sep 25 09:39:51 2018 +0100
  8. cd38e6e cpus: denver: Implement static workaround for CVE-2018-3639 by Varun Wadekar · Tue Aug 28 09:11:30 2018 -0700
  9. 2b91412 cpus: denver: reset power state to 'C1' on boot by Varun Wadekar · Mon Jun 25 11:36:47 2018 -0700
  10. 4daa1de DSU erratum 936184 workaround by John Tsichritzis · Mon Jul 23 09:11:59 2018 +0100
  11. f7f6041 Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6 by danh-arm · Thu Jul 19 17:11:32 2018 +0100
  12. 9eb5cf4 lib: cpu: Add L2 cache aux control register definition to CA72 by Konstantin Porotchkin · Thu Jul 05 11:28:02 2018 +0300
  13. a7c4687 Add initial CPU support for Cortex-Helios by Joel Hutton · Wed Jan 10 16:06:07 2018 +0000
  14. 9463cae Add initial CPU support for Cortex-Deimos by Joel Hutton · Fri May 04 15:09:47 2018 +0100
  15. 26b8589 Remove integrity check in declare_cpu_ops_base by Roberto Vargas · Fri May 04 10:54:33 2018 +0100
  16. 67762d9 Remove .struct directive by Roberto Vargas · Tue May 01 09:54:54 2018 +0100
  17. 312e17e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 by Dimitris Papastamos · Wed May 16 09:59:54 2018 +0100
  18. 7ca21db Implement Cortex-Ares 1043202 erratum workaround by Dimitris Papastamos · Mon Mar 26 16:46:01 2018 +0100
  19. 89736dd Add AMU support for Cortex-Ares by Dimitris Papastamos · Tue Feb 13 11:28:02 2018 +0000
  20. ea84d6b Add support for Cortex-Ares and Cortex-A76 CPUs by Isla Mitchell · Thu Aug 03 16:04:46 2017 +0100
  21. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  22. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  23. e6625ec Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu Apr 05 14:38:26 2018 +0100
  24. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · Fri Apr 06 15:29:34 2018 +0100
  25. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  26. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  27. 780cc95 Use PFR0 to identify need for mitigation of CVE-2017-5715 by Dimitris Papastamos · Mon Mar 12 13:27:02 2018 +0000
  28. b8d8145 Merge pull request #1282 from robertovargas-arm/misra-changes by davidcunado-arm · Wed Feb 28 18:53:30 2018 +0000
  29. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  30. 864364a MISRA fixes for Cortex A75 AMU implementation by Dimitris Papastamos · Tue Feb 27 10:55:39 2018 +0000
  31. 1be747f Refactor AMU support for Cortex A75 by Dimitris Papastamos · Wed Feb 14 10:28:36 2018 +0000
  32. 0b00f8a Factor out CPU AMU helpers by Dimitris Papastamos · Wed Feb 14 10:00:06 2018 +0000
  33. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  34. b5d1f8e Merge pull request #1200 from robertovargas-arm/bl2-el3 by davidcunado-arm · Fri Jan 19 13:40:12 2018 +0000
  35. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  36. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  37. d7e2e9e Add hooks to save/restore AMU context for Cortex A75 by Dimitris Papastamos · Mon Dec 11 11:45:35 2017 +0000
  38. fcedb69 Implement support for the Activity Monitor Unit on Cortex A75 by Dimitris Papastamos · Mon Oct 16 11:40:10 2017 +0100
  39. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  40. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  41. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  42. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  43. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  44. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  45. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  46. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  47. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  48. b83e42b CPU: Make shifted constants unsigned by Eleanor Bonnici · Wed Aug 09 10:36:08 2017 +0100
  49. ac838c5 aarch32: Fix L2CTRL definition for Cortex A57 and A72 by Dimitris Papastamos · Tue Jun 13 12:33:39 2017 +0100
  50. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  51. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  52. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  53. 805c2c7 Add support for Cortex-A75 and Cortex-A55 CPUs by David Wang · Wed Nov 09 16:29:02 2016 +0000
  54. 9326b90 Cortex-A53: add some bit definitions by Haojian Zhuang · Wed May 24 08:48:57 2017 +0800
  55. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  56. 7d99b6c Merge branch 'integration' into tf_issue_461 by Scott Branden · Sat Apr 29 08:36:12 2017 -0700
  57. bf404c0 Move defines in utils.h to utils_def.h to fix shared header compile issues by Scott Branden · Mon Apr 10 11:45:52 2017 -0700
  58. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  59. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · Thu Oct 06 16:54:53 2016 +0100
  60. 69ce101 Tegra: enable ECC/Parity protection for Cortex-A57 CPUs by Varun Wadekar · Thu May 12 13:43:33 2016 -0700
  61. d43583c cpus: denver: disable DCO operations from platform code by Varun Wadekar · Mon Feb 22 11:09:41 2016 -0800
  62. 3c337a6 cpus: Add support for all Denver variants by Varun Wadekar · Thu Sep 03 17:15:06 2015 +0530
  63. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  64. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  65. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  66. a4c219a AArch32: Add support for ARM Cortex-A32 MPCore Processor by Yatharth Kochar · Tue Jul 12 15:47:03 2016 +0100
  67. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · Tue Jun 28 16:58:26 2016 +0100
  68. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  69. 6a72a91 bl31: Add error reporting registers by Naga Sureshkumar Relli · Fri Jul 01 12:52:41 2016 +0530
  70. 63af687 Add support for ARM Cortex-A73 MPCore Processor by Yatharth Kochar · Tue Feb 09 12:00:03 2016 +0000
  71. 143ef1a Add support for Cortex-A57 erratum 833471 workaround by Sandrine Bailleux · Thu Apr 21 11:10:52 2016 +0100
  72. adcbd55 Add support for Cortex-A57 erratum 826977 workaround by Sandrine Bailleux · Thu Apr 14 14:24:13 2016 +0100
  73. 48cbe85 Add support for Cortex-A57 erratum 829520 workaround by Sandrine Bailleux · Thu Apr 14 14:18:07 2016 +0100
  74. c11116f Add support for Cortex-A57 erratum 828024 workaround by Sandrine Bailleux · Thu Apr 14 14:04:48 2016 +0100
  75. a7e0c53 Add support for Cortex-A57 erratum 826974 workaround by Sandrine Bailleux · Thu Apr 14 13:32:31 2016 +0100
  76. d481759 Disable non-temporal hint on Cortex-A53/57 by Sandrine Bailleux · Wed Jan 13 14:57:38 2016 +0000
  77. 432aa77 Add support for ARM Cortex-A35 processor by Sandrine Bailleux · Thu Jan 07 16:52:49 2016 +0000
  78. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · Mon Dec 14 09:35:25 2015 +0000
  79. 29a7a03 Juno R2: Configure the correct L2 RAM latency values by Sandrine Bailleux · Wed Nov 18 11:59:35 2015 +0000
  80. 3ce4e88 Add macros for retention control in Cortex-A53/A57 by Varun Wadekar · Fri Aug 21 15:52:51 2015 +0530
  81. 4fceaca cortex_a53: Add A53 errata #826319, #836870 by developer · Wed Jul 29 20:55:31 2015 +0800
  82. 28463b9 Add "Project Denver" CPU support by Varun Wadekar · Tue Jul 14 17:11:20 2015 +0530
  83. ea59668 Add header guards to asm macro files by Dan Handley · Wed Apr 01 17:34:24 2015 +0100
  84. c47e011 Add support for ARM Cortex-A72 processor by Vikram Kanigiri · Tue Feb 17 11:50:28 2015 +0000
  85. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  86. 798140d Juno: Implement initial platform port by Sandrine Bailleux · Thu Jul 17 16:06:39 2014 +0100
  87. 802f865 Add support for selected Cortex-A57 errata workarounds by Soby Mathew · Thu Aug 14 16:19:29 2014 +0100
  88. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  89. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100