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git01.mediatek.com / filogic / atf / b24c29ddf310843936f81a09465bcd88f67d9530 / plat / intel / soc / agilex5 / include / socfpga_plat_def.h
  1. 94f4418 Merge "feat(intel): restructure watchdog" into integration by Manish Pandey · 7 months ago
  2. e8bffd9 Merge "feat(intel): increase bl2 size limit" into integration by Manish Pandey · 7 months ago
  3. f6186b2 feat(intel): increase bl2 size limit by Jit Loon Lim · 9 months ago
  4. 6be3c34 fix(intel): revert sys counter to 400MHz by Jit Loon Lim · 10 months ago
  5. 6284537 feat(intel): restructure watchdog by Sieu Mun Tang · 1 year, 1 month ago
  6. 4c249f1 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · 1 year, 2 months ago