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git01.mediatek.com / filogic / atf / aef51b7a22038b35c87846e94dcac2618855a8ad / fdts / stm32mp157a-avenger96.dts
  1. e658cfe feat(stm32mp1-fdts): remove PLL1 settings by Gabriel Fernandez · Wed Feb 01 14:25:25 2023 +0100
  2. df4be52 feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1 by Gabriel Fernandez · Tue Aug 16 11:40:03 2022 +0200
  3. 7a4308f feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation by Lionel Debieve · Wed Feb 23 00:05:51 2022 +0100
  4. e37d905 refactor(stm32mp15-fdts): remove unused secure-status properties by Yann Gautier · Wed Mar 30 19:31:01 2022 +0200
  5. f55efba refactor(stm32mp15-fdts): remove RCC secure-status by Yann Gautier · Tue Mar 29 16:49:48 2022 +0200
  6. 9d3c53c fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver by Ahmad Fatoum · Thu Jun 02 06:28:31 2022 +0200
  7. 4ede20a fdts: stm32mp1: realign device tree with kernel by Yann Gautier · Fri Sep 18 15:04:14 2020 +0200
  8. dd445ab fdts: stm32mp1: move FDCAN to PLL4_R by Antonio Borneo · Mon Jul 29 14:46:16 2019 +0200
  9. 02a66d6 stm32mp1: Add Avenger96 board support by Manivannan Sadhasivam · Fri Apr 26 18:43:50 2019 +0530