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git01.mediatek.com / filogic / atf / ac998032fe800301dc943a193690b51b2921478c / plat / xilinx / zynqmp / bl31_zynqmp_setup.c
  1. 0fac5af Move BL_COHERENT_RAM_BASE/END defines to common_def.h by Masahiro Yamada · Wed Dec 28 16:11:41 2016 +0900
  2. 51bef61 Use *_END instead of *_LIMIT for linker derived end addresses by Masahiro Yamada · Wed Jan 18 02:10:08 2017 +0900
  3. cf4e714 zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1 by Naga Sureshkumar Relli · Fri Jul 01 12:46:43 2016 +0530
  4. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · Fri Jul 08 14:45:14 2016 -0700
  5. ecdc4d3 ARM platforms: Add support for SEPARATE_CODE_AND_RODATA by Sandrine Bailleux · Fri Jul 08 14:38:16 2016 +0100
  6. 4a1267a Introduce arm_setup_page_tables() function by Sandrine Bailleux · Wed May 18 16:11:47 2016 +0100
  7. 99c0d7b zynqmp: Add option to select between Cadence UARTs by Soren Brinkmann · Fri Jun 10 09:57:14 2016 -0700
  8. ef8f559 zynqmp: FSBL->ATF handover by Michal Simek · Mon Jun 15 14:22:50 2015 +0200
  9. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800