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git01.mediatek.com / filogic / atf / a2698373dcea36daaa4acbf7b398f4c2d60b126f / plat / xilinx / zynqmp / bl31_zynqmp_setup.c
  1. 0fac5af Move BL_COHERENT_RAM_BASE/END defines to common_def.h by Masahiro Yamada · 8 years ago
  2. 51bef61 Use *_END instead of *_LIMIT for linker derived end addresses by Masahiro Yamada · 8 years ago
  3. cf4e714 zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1 by Naga Sureshkumar Relli · 8 years ago
  4. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · 8 years ago
  5. ecdc4d3 ARM platforms: Add support for SEPARATE_CODE_AND_RODATA by Sandrine Bailleux · 8 years ago
  6. 4a1267a Introduce arm_setup_page_tables() function by Sandrine Bailleux · 8 years ago
  7. 99c0d7b zynqmp: Add option to select between Cadence UARTs by Soren Brinkmann · 8 years ago
  8. ef8f559 zynqmp: FSBL->ATF handover by Michal Simek · 9 years ago
  9. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · 9 years ago