- 64e41ba fix(versal): use correct macro name for ocm base address by Amit Nagal · 1 year, 2 months ago
- 3a7d304 feat(versal): ddr address reservation in dtb at runtime by Amit Nagal · 1 year, 4 months ago
- cc3e739 fix(versal): fix BLXX memory limits for user defined values by Ilias Apalodimas · 1 year, 6 months ago
- 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · 1 year, 7 months ago
- a63b354 refactor(versal): move set wake src fn to common place by Jay Buddhabhatti · 1 year, 8 months ago
- 6a44ad0 refactor(xilinx): rename gic macros to make common by Jay Buddhabhatti · 1 year, 8 months ago
- a0657d9 feat(versal): resolve the misra 10.1 warnings by Venkatesh Yadav Abbarapu · 2 years, 4 months ago
- 589afa5 fix(plat/xilinx/versal): resolve misra R7.2 by Abhyuday Godhasara · 3 years, 3 months ago
- abf6122 plat: xilinx: Error management support by Shubhrajyoti Datta · 3 years, 8 months ago
- b16bada xilinx: Unify Platform specific defines for PSCI module by Deepika Bhavnani · 5 years ago
- 9156ffd xilinx: versal: PLM to ATF handover by Venkatesh Yadav Abbarapu · 4 years, 10 months ago
- 5aa76f9 versal: Increase OCM memory size for DEBUG builds by Venkatesh Yadav Abbarapu · 5 years ago
- 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · 6 years ago
- 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · 6 years ago
- e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
- fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · 6 years ago