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git01.mediatek.com / filogic / atf / 9d826a1ea60fa78c96e7d2ac57bab75b4ebd4fc6 / plat / intel / soc / n5x / platform.mk
  1. ef2b295 chore: remove MULTI_CONSOLE_API references by Michal Simek · 1 year, 2 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago
  3. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  4. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 2 years, 4 months ago
  5. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years, 6 months ago
  6. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 3 years, 6 months ago
  7. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 8 months ago
  8. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 4 months ago
  9. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 8 months ago