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git01.mediatek.com / filogic / atf / 97625e3727a50dbe8f44bb092da9156d2713abad / services
  1. 97625e3 Translate secure/non-secure virtual addresses by Varun Wadekar · Fri Mar 13 14:59:03 2015 +0530
  2. a97535f Register NS shared memory for SP's activity logs and TA sessions by Varun Wadekar · Fri Mar 13 14:19:11 2015 +0530
  3. 3d4e6a5 Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd) by Varun Wadekar · Fri Mar 13 14:01:03 2015 +0530
  4. a64a854 Fix violations to the coding style by Sandrine Bailleux · Thu Mar 05 10:54:34 2015 +0000
  5. 2b7de2b Export maximum affinity using PLATFORM_MAX_AFFLVL macro by Soby Mathew · Thu Feb 12 14:45:02 2015 +0000
  6. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  7. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  8. 61e615b Verify capabilities before handling PSCI calls by Soby Mathew · Thu Jan 15 11:49:49 2015 +0000
  9. 6cdddaf Implement PSCI_FEATURES API by Soby Mathew · Wed Jan 07 11:10:22 2015 +0000
  10. 110fe36 Rework the PSCI migrate APIs by Soby Mathew · Thu Oct 23 10:35:34 2014 +0100
  11. 26fb90e Return success if an interrupt is seen during PSCI CPU_SUSPEND by Soby Mathew · Tue Jan 06 21:36:55 2015 +0000
  12. 74e52a7 Validate power_state and entrypoint when executing PSCI calls by Soby Mathew · Thu Oct 02 16:56:51 2014 +0100
  13. f512157 Save 'power_state' early in PSCI CPU_SUSPEND call by Soby Mathew · Tue Sep 30 11:19:51 2014 +0100
  14. 8595b87 Rework internal API to save non-secure entry point info by Soby Mathew · Tue Jan 06 15:36:38 2015 +0000
  15. 5f2c1b3 PSCI: Check early for invalid CPU state during CPU ON by Soby Mathew · Mon Jan 12 13:01:31 2015 +0000
  16. ffb4ab1 Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops by Soby Mathew · Fri Sep 26 15:08:52 2014 +0100
  17. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · Thu Jan 08 18:02:44 2015 +0000
  18. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · Thu Jan 08 18:02:19 2015 +0000
  19. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · Tue Nov 18 10:14:14 2014 +0000
  20. 2b69750 Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl() by Soby Mathew · Thu Oct 02 17:24:19 2014 +0100
  21. e2b2d8f Fix the array size of mpidr_aff_map_nodes_t. by Soby Mathew · Thu Dec 04 14:14:12 2014 +0000
  22. c288886 Add opteed based on tspd by Jens Wiklander · Mon Aug 04 15:39:58 2014 +0200
  23. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  24. 56bcdc2 Miscellaneous PSCI code cleanups by Achin Gupta · Mon Jul 28 00:15:23 2014 +0100
  25. f6b9e99 Add APIs to preserve highest affinity level in OFF state by Achin Gupta · Thu Jul 31 11:19:11 2014 +0100
  26. cab78e4 Rework state management in the PSCI implementation by Achin Gupta · Mon Jul 28 00:09:01 2014 +0100
  27. f3ccbab Add PSCI service specific per-CPU data by Achin Gupta · Fri Jul 25 14:52:47 2014 +0100
  28. 4dc4a47 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · Tue Aug 12 11:17:06 2014 +0100
  29. 9e46188 Merge pull request #189 from achingupta/ag/tf-issues#153 by Dan Handley · Tue Aug 19 11:04:21 2014 +0100
  30. 4fd2f5c Clarify platform porting interface to TSP by Dan Handley · Mon Aug 04 11:41:20 2014 +0100
  31. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · Mon Aug 04 23:13:10 2014 +0100
  32. 6dc22e3 Merge pull request #178 from soby-mathew/sm/optmize_el3_context by danh-arm · Mon Aug 04 10:31:54 2014 +0100
  33. 4e81341 Support asynchronous method for BL3-2 initialization by Vikram Kanigiri · Tue Jul 15 16:49:22 2014 +0100
  34. 9d70f0f Rework the TSPD setup code by Vikram Kanigiri · Tue Jul 15 16:46:43 2014 +0100
  35. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · Fri Jul 04 16:02:26 2014 +0100
  36. 5cd545d Merge pull request #177 from jcastillo-arm/jc/tf-issues/096 by danh-arm · Mon Jul 28 14:33:44 2014 +0100
  37. f558cac Rework incorrect use of assert() and panic() in codebase by Juan Castillo · Thu Jun 05 09:45:36 2014 +0100
  38. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · Fri Jul 18 18:38:28 2014 +0100
  39. 9c60d80 Remove the concept of coherent stacks by Achin Gupta · Thu Jun 26 11:12:37 2014 +0100
  40. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · Thu Jun 26 09:58:52 2014 +0100
  41. e998254 Make enablement of the MMU more flexible by Achin Gupta · Thu Jun 26 08:59:07 2014 +0100
  42. 2bc0785 Remove current CPU mpidr from PSCI common code by Andrew Thoelke · Mon Jun 09 12:44:21 2014 +0100
  43. 3c74a44 Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2 by danh-arm · Tue Jun 24 16:48:31 2014 +0100
  44. 42970b0 Merge pull request #147 from athoelke/at/remove-bakery-mpidr by danh-arm · Tue Jun 24 16:44:12 2014 +0100
  45. 2d55240 Remove all checkpatch errors from codebase by Juan Castillo · Fri Jun 13 17:05:10 2014 +0100
  46. 958cc02 Remove calling CPU mpidr from bakery lock API by Andrew Thoelke · Mon Jun 09 12:54:15 2014 +0100
  47. fb06094 Merge pull request #145 from athoelke/at/psci-memory-optimization-v2 by danh-arm · Mon Jun 23 18:04:29 2014 +0100
  48. dc589aa Merge pull request #144 from athoelke/at/init-context-v2 by danh-arm · Mon Jun 23 18:02:36 2014 +0100
  49. 56f4470 Correctly dimension the PSCI aff_map_node array by Andrew Thoelke · Fri Jun 20 00:36:14 2014 +0100
  50. e9a0d11 Eliminate psci_suspend_context array by Andrew Thoelke · Fri Jun 20 00:38:03 2014 +0100
  51. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  52. 4af473c Merge pull request #140 from athoelke/at/psci_smc_handler by danh-arm · Mon Jun 23 14:40:20 2014 +0100
  53. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · Mon Jun 02 12:38:12 2014 +0100
  54. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100
  55. a2f6553 Provide cm_get/set_context() for current CPU by Andrew Thoelke · Wed May 14 17:09:32 2014 +0100
  56. 89a3c84 PSCI SMC handler improvements by Andrew Thoelke · Tue Jun 10 16:37:37 2014 +0100
  57. 93c89ec Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · Wed May 28 17:14:36 2014 +0100
  58. 459df4c Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 into for-v0.4 by Dan Handley · Tue May 27 18:46:22 2014 +0100
  59. 701fea7 Further renames of platform porting functions by Dan Handley · Tue May 27 16:17:21 2014 +0100
  60. 3d57851 Fixup Standard SMC Resume Handling by Soby Mathew · Tue May 27 10:20:01 2014 +0100
  61. b226a4d Add enable mmu platform porting interfaces by Dan Handley · Fri May 16 14:08:45 2014 +0100
  62. ed6ff95 Split platform.h into separate headers by Dan Handley · Wed May 14 17:44:19 2014 +0100
  63. 60b13e3 Remove unused data declarations by Dan Handley · Wed May 14 15:13:16 2014 +0100
  64. a17fefa Remove extern keyword from function declarations by Dan Handley · Wed May 14 12:38:32 2014 +0100
  65. 332ff85 Merge pull request #104 from athoelke:at/tsp-entrypoints-v2 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  66. 077193f Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  67. 58484d4 Merge pull request #102 from achingupta:ag/tf-issues#104-v2 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  68. 29c7ae1 Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  69. 1c5630d Merge pull request #67 from achingupta:ag/psci_standby_bug_fix by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  70. 891c4ca Use a vector table for TSP entrypoints by Andrew Thoelke · Tue May 20 21:43:27 2014 +0100
  71. 9f71f70 Non-Secure Interrupt support during Standard SMC processing in TSP by Soby Mathew · Fri May 09 20:49:17 2014 +0100
  72. aeaab68 Add S-EL1 interrupt handling support in the TSPD by Achin Gupta · Fri May 09 13:21:31 2014 +0100
  73. 405406d Use secure timer to generate S-EL1 interrupts by Achin Gupta · Fri May 09 12:00:17 2014 +0100
  74. 9cf2bb7 Introduce interrupt handling framework in BL3-1 by Achin Gupta · Fri May 09 11:07:09 2014 +0100
  75. 27b895e Add context library API to change a bit in SCR_EL3 by Achin Gupta · Sun May 04 18:38:28 2014 +0100
  76. 18d6eaf Rework 'state' field usage in per-cpu TSP context by Achin Gupta · Sun May 04 18:23:26 2014 +0100
  77. d8c9d26 Rework memory information passing to BL3-x images by Vikram Kanigiri · Fri May 16 18:48:12 2014 +0100
  78. da56743 Populate BL31 input parameters as per new spec by Vikram Kanigiri · Tue Apr 15 18:08:08 2014 +0100
  79. 9851e42 Introduce macros to manipulate the SPSR by Vikram Kanigiri · Tue May 13 14:42:08 2014 +0100
  80. 5e5c207 Rework BL3-1 unhandled exception handling and reporting by Soby Mathew · Mon Apr 07 15:28:55 2014 +0100
  81. 42c5280 Fix broken standby state implementation in PSCI by Achin Gupta · Fri May 09 19:32:25 2014 +0100
  82. 74a62b3 fvp: Provide per-EL MMU setup functions by Sandrine Bailleux · Fri May 09 11:35:36 2014 +0100
  83. 9ceff0f Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1 by danh-arm · Thu May 08 12:25:02 2014 +0100
  84. 6c5192a Preserve x19-x29 across world switch for exception handling by Soby Mathew · Wed Apr 30 15:36:37 2014 +0100
  85. f977ed8 Access system registers directly in assembler by Andrew Thoelke · Mon Apr 28 12:32:02 2014 +0100
  86. 42e75a7 Correct usage of data and instruction barriers by Andrew Thoelke · Mon Apr 28 12:28:39 2014 +0100
  87. a4cb68e Remove variables from .data section by Dan Handley · Wed Apr 23 13:47:06 2014 +0100
  88. 2bd4ef2 Reduce deep nesting of header files by Dan Handley · Wed Apr 09 13:14:54 2014 +0100
  89. e2712bc Always use named structs in header files by Dan Handley · Thu Apr 10 15:37:22 2014 +0100
  90. 27f6e7d Move PSCI global functions out of private header by Dan Handley · Wed Apr 23 15:22:18 2014 +0100
  91. bcd60ba Separate BL functions out of arch.h by Dan Handley · Thu Apr 17 18:53:42 2014 +0100
  92. f3c8f32 Separate out CASSERT macro into own header by Dan Handley · Thu Apr 17 17:29:58 2014 +0100
  93. 176e7b4 Remove vpath usage in makefiles by Dan Handley · Tue Apr 15 18:20:09 2014 +0100
  94. 714a0d2 Make use of user/system includes more consistent by Dan Handley · Wed Apr 09 13:13:04 2014 +0100
  95. a70615f Move include and source files to logical locations by Dan Handley · Wed Apr 09 12:48:25 2014 +0100
  96. f100f41 Preserve PSCI cpu_suspend 'power_state' parameter. by Vikram Kanigiri · Tue Apr 01 19:26:26 2014 +0100
  97. 38bde41 Place assembler functions in separate sections by Andrew Thoelke · Tue Mar 18 13:46:55 2014 +0000
  98. c7f2069 Fix build failure due to a typo in TSPD code by Achin Gupta · Wed Mar 26 18:44:15 2014 +0000
  99. 1734119 Fix build by correcting asm helper function usage in TSPD by Vikram Kanigiri · Mon Mar 24 11:21:35 2014 +0000
  100. 3b7c59b Add standby state support in PSCI cpu_suspend api by Vikram Kanigiri · Fri Mar 21 11:57:10 2014 +0000