Log - 974e3a1e6f8bcf8c25d8696b0590ba5865d57bfa - filogic/atf

9e505f9 refactor(cpufeat): add macro to simplify is_feat_xx_present by Sona Mathew · Wed Mar 13 11:33:54 2024 -0500
e76dd30 Merge "fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32" into integration by Yann Gautier · Fri Apr 19 14:04:52 2024 +0200
564c286 fix(cm): hide `cm_init_context_by_index` from BL1 by Chris Kay · Tue Feb 06 15:43:40 2024 +0000
9275559 fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32 by Ahmad Fatoum · Tue Mar 12 18:36:46 2024 +0100
eee28e7 chore: update to use Arm word across TF-A by Govindraj Raja · Tue Aug 01 15:52:40 2023 -0500
6468d4a refactor(cpufeat): separate the EL2 and EL3 enablement code by Boyan Karatotev · Thu Feb 16 15:12:45 2023 +0000
05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · Wed Feb 15 13:21:50 2023 +0000
906776e refactor(amu): use new AMU feature check routines by Andre Przywara · Fri Mar 03 10:30:06 2023 +0000
0b7f1b0 refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1 by Andre Przywara · Tue Mar 21 13:53:19 2023 +0000
44e33e0 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
06ea44e refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 17:30:43 2022 +0000
f92c0cb refactor(context mgmt): add cm_prepare_el3_exit_ns function by Zelalem Aweke · Mon Jan 31 16:59:42 2022 -0600
51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · Thu Jul 08 09:33:18 2021 +0100
f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · Tue Jun 29 11:44:20 2021 +0100
7d0299f fix: random typos in tf-a code base by Olivier Deprez · Tue May 25 12:06:03 2021 +0200
87675d4 Coverity: remove unnecessary header file includes by Zelalem · Mon Feb 03 14:56:42 2020 -0600
9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 20 15:22:44 2019 +0100
e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
28dce9e context_mgmt: Make cm_init_context_common public by Antonio Nino Diaz · Tue May 22 10:09:10 2018 +0100
3c817f4 Rename 'smcc' to 'smccc' by Antonio Nino Diaz · Wed Mar 21 10:49:27 2018 +0000
dda48b0 AMU: Implement support for aarch32 by Dimitris Papastamos · Tue Oct 17 14:03:14 2017 +0100
1e6f93e Factor out extension enabling to a separate function by Dimitris Papastamos · Tue Nov 07 09:55:29 2017 +0000
97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
a8954fc Replace some memset call by zeromem by Douglas Raillard · Thu Jan 26 15:54:44 2017 +0000
adb7027 AArch32: Fix the stack alignment issue by Soby Mathew · Tue Dec 06 12:10:51 2016 +0000
c14b08e Reset EL2 and EL3 configurable controls by David Cunado · Fri Nov 25 00:21:59 2016 +0000
5f55e28 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR by David Cunado · Mon Oct 31 17:37:34 2016 +0000
a993c42 Unify SCTLR initialization for AArch32 normal world by Soby Mathew · Thu Sep 29 14:15:57 2016 +0100
b4a970a AArch32: Fix SCTLR context initialization by Soby Mathew · Wed Aug 31 12:34:33 2016 +0100
748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100