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git01.mediatek.com / filogic / atf / 971e29fe8867f32d99ccd25876fd3e2ec76e3619 / include / arch / aarch32
  1. 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · Thu Feb 16 09:45:29 2023 +0000
  2. 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · Wed Feb 15 13:21:50 2023 +0000
  3. 4af0d99 Merge "fix(qemu): fix 32-bit builds with stack protector" into integration by Manish Pandey · Wed Jun 07 10:50:16 2023 +0200
  4. a8d525e Merge changes from topic "dummy_feat_aa32" into integration by Manish Pandey · Tue Jun 06 16:50:36 2023 +0200
  5. e7d7c27 refactor(cpus): move cpu_ops field defines to a header by Boyan Karatotev · Wed Jan 25 16:55:18 2023 +0000
  6. 821d6c2 fix(qemu): fix 32-bit builds with stack protector by Andre Przywara · Tue May 23 10:34:38 2023 +0100
  7. dc3fcdf feat(cpufeat): deny AArch64-only features when building for AArch32 by Andre Przywara · Tue May 23 10:34:38 2023 +0100
  8. 54d5791 feat(cpufeat): add AArch32 PAN detection support by Andre Przywara · Tue May 23 13:56:55 2023 +0100
  9. 9b468c3 Merge changes I1bfa797e,I0ec7a70e into integration by Manish Pandey · Tue May 09 22:05:52 2023 +0200
  10. 2be03c0 fix(tree): correct some typos by Elyes Haouas · Mon Feb 13 09:14:48 2023 +0100
  11. 7fe0352 feat(errata_abi): errata management firmware interface by Sona Mathew · Fri Nov 18 18:05:38 2022 -0600
  12. 1f55c41 refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED by Andre Przywara · Thu Jan 26 16:47:52 2023 +0000
  13. 906776e refactor(amu): use new AMU feature check routines by Andre Przywara · Fri Mar 03 10:30:06 2023 +0000
  14. 44e33e0 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  15. f3e8cfc refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  16. 4f8eada Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration by Manish Pandey · Wed Mar 15 12:45:26 2023 +0100
  17. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  18. 183638f style: remove useless trailing semicolon and line continuations by Elyes Haouas · Mon Feb 13 10:05:41 2023 +0100
  19. 06ea44e refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 17:30:43 2022 +0000
  20. bb0db3b refactor(cpufeat): wrap CPU ID register field isolation by Andre Przywara · Wed Jan 25 12:26:14 2023 +0000
  21. 69508e9 feat(debug): add AARCH32 CP15 fault registers by Yann Gautier · Tue May 21 18:59:18 2019 +0200
  22. d4e2503 feat(gic): add APIs to raise NS and S-EL1 SGIs by Florian Lugou · Wed Sep 08 12:40:24 2021 +0200
  23. 0824b45 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · Thu Feb 24 10:47:33 2022 +0800
  24. 74b7e44 feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX by johpow01 · Wed Dec 01 13:18:30 2021 -0600
  25. a40141d refactor(amu): detect architected counters at runtime by Chris Kay · Tue May 25 12:33:18 2021 +0100
  26. a5fde28 refactor(amu): factor out register accesses by Chris Kay · Wed May 26 11:58:23 2021 +0100
  27. b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · Fri Oct 15 17:25:52 2021 -0500
  28. 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · Thu Jul 08 09:33:18 2021 +0100
  29. 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · Sun Jul 18 02:26:27 2021 +0100
  30. f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · Tue Jun 29 11:44:20 2021 +0100
  31. f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · Wed Jul 07 16:27:10 2021 +0100
  32. 514e59c Add PIE support for AARCH32 by Yann Gautier · Mon Oct 05 11:02:54 2020 +0200
  33. e57bce8 Avoid the use of linker *_SIZE__ macros by Yann Gautier · Tue Aug 18 14:42:41 2020 +0200
  34. 08fec33 arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms by Chris Kay · Tue Mar 09 13:34:35 2021 +0000
  35. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · Fri Oct 02 13:41:11 2020 -0500
  36. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · Mon Nov 23 18:38:15 2020 +0000
  37. 5c29cba aarch64/arm: Add compiler barrier to barrier instructions by Andre Przywara · Fri Oct 16 18:19:03 2020 +0100
  38. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · Tue Aug 04 16:18:52 2020 -0500
  39. 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · Tue Jul 14 08:17:56 2020 +0100
  40. 90d6532 Provide a hint to power controller for DSU cluster power down by Madhukar Pappireddy · Wed Oct 30 14:24:39 2019 -0500
  41. 019b4f8 locks: bakery: use is_dcache_enabled() helper by Masahiro Yamada · Thu Apr 02 15:35:19 2020 +0900
  42. a5c6636 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · Fri Mar 20 14:21:05 2020 -0500
  43. 84d681f Merge "el3_entrypoint_common: avoid overwriting arg3" into integration by Manish Pandey · Thu Mar 19 22:35:13 2020 +0000
  44. bfe7bb6 Use Speculation Barrier instruction for v8.5 cores by Madhukar Pappireddy · Tue Mar 10 18:04:59 2020 -0500
  45. fcbcd6f aarch32: stop speculative execution past exception returns by Madhukar Pappireddy · Wed Feb 26 12:37:05 2020 -0600
  46. c241b57 el3_entrypoint_common: avoid overwriting arg3 by Yann Gautier · Tue Jan 28 11:45:38 2020 +0100
  47. 20be077 Changes to support updated register usage in SMCCC v1.2 by Madhukar Pappireddy · Sat Nov 09 23:28:08 2019 -0600
  48. d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · Mon May 27 09:32:00 2019 +0200
  49. 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 20 15:22:44 2019 +0100
  50. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  51. 5553417 SSBS: init SPSR register with default SSBS value by John Tsichritzis · Tue Jul 23 11:12:41 2019 +0100
  52. 35e08da console: update skeleton by Ambroise Vincent · Fri May 31 16:21:59 2019 +0100
  53. 007d745 arch: add some defines for generic timer registers by Yann Gautier · Wed Apr 17 13:47:07 2019 +0200
  54. 457c64e aarch32: Allow compiling with soft-float toolchain by Manish Pandey · Mon Apr 01 15:27:18 2019 +0100
  55. 0a0ca8b Console: remove deprecated finish_console_register by Ambroise Vincent · Wed Mar 27 15:45:35 2019 +0000
  56. f5fdfbc Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · Thu Feb 21 14:16:24 2019 +0000
  57. 404184d Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd by Antonio Niño Díaz · Wed Feb 27 09:21:42 2019 +0000
  58. 078e66f plat/arm: Support for Cortex A5 in FVP Versatile Express platform by Usama Arif · Wed Dec 12 17:14:29 2018 +0000
  59. b69ac08 Division functionality for cores that dont have divide hardware. by Usama Arif · Wed Dec 12 17:08:33 2018 +0000
  60. 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · Mon Feb 18 16:55:43 2019 +0000
  61. d29d21e drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · Wed Feb 06 09:23:04 2019 +0000
  62. c326c34 xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · Fri Jan 11 11:20:10 2019 +0000
  63. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  64. 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · Mon Dec 17 17:20:57 2018 +0000