Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 928e60f3dfcdc2d2730fa89553db7bfac2628a06 / lib / el3_runtime
  1. f00da74 RAS: Add fault injection support by Jeenu Viswambharan · Fri Dec 08 12:13:51 2017 +0000
  2. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · Wed Apr 04 16:07:11 2018 +0100
  3. 23d05a8 AArch64: Refactor GP register restore to separate function by Jeenu Viswambharan · Wed Nov 29 16:59:34 2017 +0000
  4. 3c817f4 Rename 'smcc' to 'smccc' by Antonio Nino Diaz · Wed Mar 21 10:49:27 2018 +0000
  5. ce88eee Enable SVE for Non-secure world by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  6. dda48b0 AMU: Implement support for aarch32 by Dimitris Papastamos · Tue Oct 17 14:03:14 2017 +0100
  7. e08005a AMU: Implement support for aarch64 by Dimitris Papastamos · Thu Oct 12 13:02:29 2017 +0100
  8. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
  9. 1e6f93e Factor out extension enabling to a separate function by Dimitris Papastamos · Tue Nov 07 09:55:29 2017 +0000
  10. d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  11. a7921b9 aarch64: Add PubSub events to capture security state transitions by Dimitris Papastamos · Fri Oct 13 15:27:58 2017 +0100
  12. 4168f2f Init and save / restore of PMCR_EL0 / PMCR by David Cunado · Mon Oct 02 17:41:39 2017 +0100
  13. 878f03c Merge pull request #1019 from etienne-lms/log-size by davidcunado-arm · Thu Sep 07 00:40:59 2017 +0100
  14. 97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
  15. 00eac15 fix a typo about sctlr_el2 by Ken Kuang · Wed Aug 23 16:03:29 2017 +0800
  16. ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
  17. fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
  18. 6715485 Merge pull request #927 from jeenu-arm/state-switch by davidcunado-arm · Thu May 11 16:04:52 2017 +0100
  19. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  20. 2a9b882 Add macro to check whether the CPU implements an EL by Jeenu Viswambharan · Tue Feb 21 14:40:44 2017 +0000
  21. a8954fc Replace some memset call by zeromem by Douglas Raillard · Thu Jan 26 15:54:44 2017 +0000
  22. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  23. adb7027 AArch32: Fix the stack alignment issue by Soby Mathew · Tue Dec 06 12:10:51 2016 +0000
  24. c14b08e Reset EL2 and EL3 configurable controls by David Cunado · Fri Nov 25 00:21:59 2016 +0000
  25. 5f55e28 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR by David Cunado · Mon Oct 31 17:37:34 2016 +0000
  26. a993c42 Unify SCTLR initialization for AArch32 normal world by Soby Mathew · Thu Sep 29 14:15:57 2016 +0100
  27. b4a970a AArch32: Fix SCTLR context initialization by Soby Mathew · Wed Aug 31 12:34:33 2016 +0100
  28. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  29. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000