Log - 9286c021b599a9114222558115f8aaca29f0d119 - filogic/atf

7cac3de (feat)n1sdp: add support for OP-TEE SPMC by Vishnu Banavath · Mon Jun 20 18:20:21 2022 +0100
f1c8861 feat(n1sdp): add support for nt_fw_config by sahil · Tue Mar 15 14:11:43 2022 +0530
6ec01e8 feat(n1sdp): enable trusted board boot on n1sdp by sah01 · Sun Jun 06 14:38:01 2021 +0530
9faad3c Add support for Neoverse-N2 CPUs. by Javier Almansa Sobrino · Fri Oct 23 13:22:07 2020 +0100
fcf6852 n1sdp: remote chip SPI numbering for multichip GIC routing by Sayanta Pattanayak · Fri Jul 31 12:59:24 2020 +0530
c2db651 fdts: n1sdp: DTS file for single-chip and multi-chip environment. by Andre Przywara · Mon Jul 06 11:19:41 2020 +0530
e1cc130 GICv3: GIC-600: Detect GIC-600 at runtime by Andre Przywara · Wed Mar 25 15:50:38 2020 +0000
84f1b5d TF-A GICv3 driver: Introduce makefile by Alexei Fedorov · Mon Mar 23 18:45:17 2020 +0000
1852eba Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integration by Manish Pandey · Thu Mar 12 10:09:31 2020 +0000
b912087 n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag by Chandni Cherukuri · Thu Mar 05 11:49:57 2020 +0530
2f13d6c TF-A GICv3 driver: Separate GICD and GICR accessor functions by Alexei Fedorov · Fri Feb 21 10:17:26 2020 +0000
7f8837b drivers/arm/scmi: allow use of multiple SCMI channels by Aditya Angadi · Tue Dec 31 14:23:53 2019 +0530
7b424ba drivers/mhu: derive doorbell base address by Aditya Angadi · Tue Dec 31 10:14:32 2019 +0530
0ac3941 GIC-600: Fix include ordering according to the coding style by Max Shvetsov · Tue Nov 19 11:01:26 2019 +0000
2c44a44 n1sdp: setup multichip gic routing table by Manish Pandey · Mon Oct 14 17:37:38 2019 +0100
b68e286 n1sdp: update platform macros for dual-chip setup by Manish Pandey · Wed Sep 11 17:07:40 2019 +0100
2f3203f n1sdp: introduce platform information SDS region by Manish Pandey · Mon Oct 07 17:47:46 2019 +0100
8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
75e4ccb n1sdp: fix DMC ECC enablement sequence in N1SDP platform by Manoj Kumar · Mon Jul 22 16:10:12 2019 +0100
69bebd8 n1sdp: add code for DDR ECC enablement and BL33 copy to DDR by Manoj Kumar · Fri Jun 21 17:07:13 2019 +0100
2f3365b N1SDP: Fix DRAM2 start address by Sami Mujawar · Thu May 09 13:43:30 2019 +0100
20b4841 plat/arm: introduce wrapper functions to setup secure watchdog by Aditya Angadi · Tue Apr 16 11:29:14 2019 +0530
0d31688 plat/arm: mhu: make mhu driver generic by Masahisa Kojima · Thu Mar 07 11:23:42 2019 +0900
947fea0 Merge pull request #1835 from jts-arm/rename by Antonio Niño Díaz · Fri Feb 22 13:05:37 2019 +0000
56369c1 Rename Cortex-Ares to Neoverse N1 by John Tsichritzis · Tue Feb 19 13:49:06 2019 +0000
81eb5ce Rename PLAT_ARM_BL31_RUN_UART* variable by Usama Arif · Mon Feb 11 16:35:42 2019 +0000
1b0c6f1 plat/arm: mhu: Move to drivers/ folder by Antonio Nino Diaz · Wed Jan 23 21:08:43 2019 +0000
c30db5b plat/arm: scmi: Move to drivers/ folder by Antonio Nino Diaz · Wed Jan 23 20:37:32 2019 +0000
bd7b740 plat/arm: Sanitise includes by Antonio Nino Diaz · Fri Jan 25 14:30:04 2019 +0000
a320ecd plat/arm: Fix header dependencies by Antonio Nino Diaz · Tue Jan 15 14:19:50 2019 +0000
b66a18e plat/arm/n1sdp: define the uart constants for N1SDP by Deepak Pandey · Tue Dec 18 17:10:24 2018 +0530
e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
059ca72 Merge pull request #1699 from chandnich/sgi-mt-support by Soby Mathew · Mon Dec 03 13:29:33 2018 +0000
e4bf6a0 plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' function by Chandni Cherukuri · Wed Nov 14 13:43:59 2018 +0530
0fdcbc0 plat/css: allow platforms to define the system power domain level by Chandni Cherukuri · Tue Oct 16 15:19:54 2018 +0530
5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
9cbacf6 plat/arm: Introduce the N1SDP. by Deepak Pandey · Wed Aug 08 10:32:51 2018 +0530