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git01.mediatek.com / filogic / atf / 9164ec0adea1b2004187a2d4c2cd3367e0f8d89a / plat / nvidia / tegra / soc / t210
  1. 92cea4a tegra: Fix mmap_region_t struct mismatch by Andreas Färber · Sat Feb 17 06:02:32 2018 +0100
  2. e363146 Fix order of remaining platform #includes by Isla Mitchell · Fri Jul 14 10:46:32 2017 +0100
  3. 66231d1 Tegra: enable 'signed-comparison' compilation warning/errors by Varun Wadekar · Wed Jun 07 09:57:42 2017 -0700
  4. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  5. b91b5fc Tegra210: implement 'get_target_pwr_state' handler by Varun Wadekar · Tue Apr 18 11:22:01 2017 -0700
  6. 4d160ac Tegra: memmap Tegra micro-seconds timer controller by Steven Kao · Fri Dec 23 16:05:13 2016 +0800
  7. 1108fc6 plat/tegra: Enable Cortex-A53 erratum 855873 workaround by Andre Przywara · Mon Nov 07 10:53:14 2016 +0000
  8. ed3c62b Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs by Varun Wadekar · Mon Mar 06 09:15:15 2017 -0800
  9. 20e9fef Tegra210: assert if afflvl0/1 have incorrect state-ids by Harvey Hsieh · Wed Dec 28 21:53:18 2016 +0800
  10. 1edb882 Tegra210: new TZDRAM base address by Varun Wadekar · Thu Sep 01 14:59:32 2016 -0700
  11. dba8007 Tegra210: set core power state during cluster power down by Varun Wadekar · Thu Sep 01 14:56:17 2016 -0700
  12. b7b4575 Tegra: GIC: enable FIQ interrupt handling by Varun Wadekar · Mon Dec 28 14:55:41 2015 -0800
  13. 6eec6d6 Tegra: allow individual SoCs to restore their settings by Varun Wadekar · Thu Mar 03 13:28:10 2016 -0800
  14. 6077dce Tegra: enable PSCI extended state ID processing by Varun Wadekar · Wed Jan 27 11:31:06 2016 -0800
  15. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · Wed Dec 09 18:18:53 2015 -0800
  16. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · Thu Oct 29 10:37:28 2015 +0530
  17. 7a9a285 Tegra: Memory Controller Driver (v1) by Varun Wadekar · Fri Sep 18 11:21:22 2015 +0530
  18. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · Tue Sep 22 13:33:56 2015 +0530
  19. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · Wed Sep 09 11:29:24 2015 +0530
  20. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · Thu Sep 03 14:32:44 2015 +0530
  21. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · Tue Aug 25 17:01:06 2015 +0530
  22. e82e29c Implement plat_get_syscnt_freq2 on platforms by Antonio Nino Diaz · Thu May 19 10:00:28 2016 +0100
  23. 3c0087a Move `plat_get_syscnt_freq()` to arm_common.c by Yatharth Kochar · Thu Apr 14 14:49:37 2016 +0100
  24. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · Fri Aug 07 10:03:00 2015 +0530
  25. 8b82fae Tegra: introduce per-soc system reset handler by Varun Wadekar · Mon Nov 09 17:39:28 2015 -0800
  26. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · Fri Aug 21 15:56:02 2015 +0530
  27. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · Mon Jul 27 13:00:50 2015 +0530
  28. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · Thu Jul 23 10:07:54 2015 +0530
  29. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · Tue Jul 21 11:53:35 2015 +0530
  30. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · Thu Jul 16 09:46:28 2015 +0530
  31. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · Thu Jul 16 11:58:19 2015 +0530
  32. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · Wed Jul 08 17:42:02 2015 +0530
  33. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · Fri Jul 03 16:31:28 2015 +0530
  34. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530