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git01.mediatek.com / filogic / atf / 8c178b58e65d69c855cad07800b31b28ed732de8 / plat / rockchip / rk3399 / drivers / pmu / m0_ctl.c
  1. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  2. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · Fri Apr 20 15:55:21 2018 +0800
  3. e363146 Fix order of remaining platform #includes by Isla Mitchell · Fri Jul 14 10:46:32 2017 +0100
  4. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  5. 22a9871 rockchip: rk3399: Clean up and seprate secure parts from SoC codes by Xing Zheng · Fri Feb 24 14:56:41 2017 +0800
  6. 8140b7d rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error by Lin Huang · Fri Dec 30 13:53:25 2016 +0800
  7. 61230b0 FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init by Xing Zheng · Tue Dec 20 20:44:41 2016 +0800
  8. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · Mon Dec 12 15:18:08 2016 +0800
  9. c8e5c78 rockchip: rk3399: fix hang in ddr set rate by Derek Basehore · Fri Feb 24 14:33:03 2017 +0800
  10. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · Wed Oct 26 21:25:26 2016 +0800