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git01.mediatek.com / filogic / atf / 76c3f5b3e791261835e0206ee34680949f11dac2 / plat / intel / soc / n5x
  1. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 7 months ago
  2. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 3 years, 3 months ago
  3. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 3 years, 6 months ago
  4. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 8 months ago
  5. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 8 months ago
  6. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 4 months ago
  7. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 8 months ago