Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
atf
/
75b3f47bc906265f81bdd1bc5df430979a441826
/
plat
/
intel
/
soc
/
stratix10
/
include
/
s10_clock_manager.h
60f7fb8
fix(intel): revert back to use L4 clock
by Sieu Mun Tang
· 8 months ago
ffa06e7
fix(intel): fix hardcoded mpu frequency ticks
by Jit Loon Lim
· 1 year, 2 months ago
28c1c78
feat(intel): restructure sys mgr for S10/N5X
by Jit Loon Lim
· 1 year, 3 months ago
f48707a
feat(intel): implement timer init divider via CPU frequency for N5X
by Sieu Mun Tang
· 2 years, 2 months ago
1a832bf
Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration
by Madhukar Pappireddy
· 2 years, 4 months ago
a4a4327
feat(intel): implement timer init divider via cpu frequency. (#1)
by BenjaminLimJL
· 2 years, 5 months ago
e026eea
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC
by Sieu Mun Tang
· 2 years, 4 months ago
9f5dfc9
intel: Refactor common platform code [1/5]
by Hadi Asyrafi
· 4 years, 10 months ago
78fee35
intel: stratix10: Fix reliance on hard coded clock information
by Hadi Asyrafi
· 5 years ago
c0d4d93
intel: Enable watchdog timer on Intel S10 platform
by Muhammad Hadi Asyrafi Abdul Halim
· 5 years ago
59400a4
plat: intel: Add BL2 support for Stratix 10 SoC
by Loh Tien Hock
· 6 years ago