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git01.mediatek.com / filogic / atf / 72a4b69e24109b79a4792c069d08af288b2b92d2 / plat / rockchip / rk3399 / drivers / m0 / src
  1. 397046c rockchip: rk3399: Move DQS drive strength setting to M0 by Derek Basehore · 7 years ago
  2. b4bcc1d rockchip: Clean up header and referenced files by Xing Zheng · 7 years ago
  3. fc0552d rockchip: rk3399: Don't wait for vblank in M0 for ddrfreq by Derek Basehore · 8 years ago
  4. 2510366 rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfs by Lin Huang · 8 years ago
  5. 3b0eb7e rockchip: rk3399: check vop status when we wait dma finish flag by Lin Huang · 8 years ago
  6. e7c2422 rockchip: rk3399: add stopwatch functions to m0 by Lin Huang · 8 years ago
  7. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · 8 years ago
  8. aae6be4 rockchip: update the raw read/write APIs for M0 by Xing Zheng · 8 years ago
  9. b400374 rockchip: add M0 source code and build system for RK3399 by Caesar Wang · 8 years ago