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git01.mediatek.com / filogic / atf / 6f9d19e1a1d9ce268a71936ee284c71ef98e7ab7 / plat / marvell / armada / a3k / common / include
  1. bb63a1c feat(plat/marvell/a3k): add north and south bridge reset registers by Pali Rohár · 3 years ago
  2. 52c1de5 fix(plat/marvell/a3720/uart): fix UART parent clock rate determination by Pali Rohár · 3 years, 6 months ago
  3. 168d81e refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros by Pali Rohár · 3 years, 6 months ago
  4. 206c8cf refactor(plat/marvell/uart): remove unused macros by Pali Rohár · 3 years, 6 months ago
  5. 2666c1e fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation by Pali Rohár · 3 years, 6 months ago
  6. 5fd234e plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB by Marek Behún · 3 years, 10 months ago
  7. 19d8578 plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor by Marek Behún · 3 years, 10 months ago
  8. a3ae7fa plat: marvell: armada: a3k: allow image load to RAM address 0 by Konstantin Porotchkin · 5 years ago
  9. b5fa64a plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS by Konstantin Porotchkin · 6 years ago
  10. d2a19cc plat: marvell: armada: reduce memory size reserved for FIP image by Marcin Wojtas · 4 years, 5 months ago
  11. 5f8630b plat: marvell: armada: platform definitions cleanup by Konstantin Porotchkin · 4 years, 5 months ago
  12. 459366b plat: marvell: armada: re-enable BL32_BASE definition by Konstantin Porotchkin · 6 years ago
  13. 45f1655 plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs by Marcin Wojtas · 4 years, 5 months ago