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git01.mediatek.com / filogic / atf / 6da8794fe06db376f58dda601e3668d2670c2bc1 / plat / xilinx / versal_net / versal_net_gicv3.c
  1. 6da8794 fix(xilinx): rename macros to align with ARM by Jay Buddhabhatti · 1 year, 1 month ago
  2. 0129707 feat(xilinx): sync copyright format by Michal Simek · 1 year, 7 months ago
  3. 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · 1 year, 7 months ago
  4. 6a44ad0 refactor(xilinx): rename gic macros to make common by Jay Buddhabhatti · 1 year, 9 months ago
  5. 33bfc5e build: always prefix section names with `.` by Chris Kay · 1 year, 9 months ago
  6. d517f7b fix(versal-net): populate gic v3 rdist data statically by Jay Buddhabhatti · 1 year, 10 months ago
  7. c6daff0 feat(versal-net): add support for platform management by Jay Buddhabhatti · 2 years, 2 months ago
  8. 9179436 feat(versal-net): add support for Xilinx Versal NET platform by Michal Simek · 2 years, 3 months ago