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git01.mediatek.com / filogic / atf / 6aa8e9adb3336c0443eb37c471da16c17aad9d4c / plat / xilinx / versal / include / platform_def.h
  1. 64e41ba fix(versal): use correct macro name for ocm base address by Amit Nagal · Tue Aug 29 02:44:58 2023 -1200
  2. 3a7d304 feat(versal): ddr address reservation in dtb at runtime by Amit Nagal · Mon Jul 10 10:32:15 2023 +0530
  3. cc3e739 fix(versal): fix BLXX memory limits for user defined values by Ilias Apalodimas · Tue May 23 14:46:48 2023 +0300
  4. 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · Fri Apr 14 08:43:51 2023 +0200
  5. a63b354 refactor(versal): move set wake src fn to common place by Jay Buddhabhatti · Tue Feb 28 02:22:02 2023 -0800
  6. 6a44ad0 refactor(xilinx): rename gic macros to make common by Jay Buddhabhatti · Tue Feb 28 01:23:04 2023 -0800
  7. a0657d9 feat(versal): resolve the misra 10.1 warnings by Venkatesh Yadav Abbarapu · Wed Jul 20 09:03:22 2022 +0530
  8. 589afa5 fix(plat/xilinx/versal): resolve misra R7.2 by Abhyuday Godhasara · Wed Aug 11 06:15:13 2021 -0700
  9. abf6122 plat: xilinx: Error management support by Shubhrajyoti Datta · Wed Mar 17 23:01:17 2021 +0530
  10. b16bada xilinx: Unify Platform specific defines for PSCI module by Deepika Bhavnani · Fri Dec 13 10:53:56 2019 -0600
  11. 9156ffd xilinx: versal: PLM to ATF handover by Venkatesh Yadav Abbarapu · Wed Jan 22 21:23:20 2020 -0700
  12. 5aa76f9 versal: Increase OCM memory size for DEBUG builds by Venkatesh Yadav Abbarapu · Mon Nov 25 01:47:48 2019 -0700
  13. 54d1319 xilinx: versal: Add PSCI APIs for suspend/resume by Tejas Patel · Wed Feb 27 18:44:55 2019 +0530
  14. 0a2f9ad plat: xilinx: versal: Move versal_def.h to include directory by Tejas Patel · Fri Dec 14 00:55:30 2018 -0800
  15. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  16. fe4af66 arm64: versal: Add support for new Xilinx Versal ACAPs by Siva Durga Prasad Paladugu · Tue Sep 25 18:44:58 2018 +0530